1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device to enhance the characteristic of a dual-gate MOS.
2. Discussion of Related Art
Generally speaking, a dual-gate MOS used in the process for below 0.25 .mu.m level circuit has two gate electrodes. The MOS has its drain electrode connected to the source electrode of another MOS.
The dual-gate MOS confers the advantage that stable operation is performed without much internal feedback at a very high frequency, and, that a second gate electrode is available to an AGC (Auto Gain Control), thus producing little change in the input/output impedances with a good characteristic of cross modulation.
FIGS. 1a-1f illustrate a method of manufacturing a dual-gate MOS of the prior art.
As shown in FIG. 1a, a gate oxide layer 12 is grown on a p-type semiconductor substrate 11 with a thermal oxidation. On the gate oxide layer 12 is formed polysilicon 13a in the 2000 to 2500 .ANG. range of thickness.
As shown in FIG. 1b, a first photoresist 14 is deposited on the polysilicon 13a, and it is selectively exposed and developed, removing only a portion of the first photoresist 14 where a first gate electrode will be formed. Following the exposure and development, p-type impurities are ion-implanted into the polysilicon 13a by using the first photoresist 14 as a mask in the 10.sup.13 to 10.sup.15 range of concentration and at the 10 to 15 KeV pressure. The p-type impurities are usually boron (B) ions.
As shown in FIG. 1c, the first photoresist 14 is removed and a second photoresist 15 is formed on the polysilicon 13a selectively doped with p-type impurities. The polysilicon 13a is selectively exposed and developed, removing only a portion where a second gate electrode will be formed. Using the second photoresist 15 as a mask, n-type impurities are ion-implanted into the polysilicon 13a in the 10.sup.13 to 10.sup.15 range of concentration and at the 10 to 15 KeV pressure. The n-type impurities are usually P ions.
As shown in FIG. 1d, following a removal of the second photoresist 15, the whole surface is cleaned and processed in an annealing which is performed for 20 to 40 minutes at the 700 to 900.degree. C. temperature in the nitrogen (N.sub.2) atmosphere.
On the polysilicon 13a annealed is sequentially formed a BARC 16 and a third photoresist 17. The third photoresist 17 is selectively exposed and developed, leaving only a portion where first and second gate electrodes will be formed.
As shown in FIG. 1e, using the third photoresist 17 as a mask, the polysilicon 13a is selectively etched at a back pressure above 8 Torr in a Cl.sub.2 /O.sub.2 and HBr/Cl.sub.2 atmosphere, for the purpose of protecting the third photoresist 17 from being burnt and producing a cooling effect in the maximum, thus forming first and second gate electrodes 13b and 13c. To produce polymer to the maximum in the etching process of the polysilicon 13a, a lateral etching is suppressed by adjusting the ratio of the mixed gas HBr/Cl.sub.2 to more than 2:1. The back pressure produced is from He gas.
As shown in FIG. 1f, the third photoresist 17 and the BARC 16 are removed. The whole surface is doped with n-type impurities by using the first and second gate electrodes 13b and 13c as a mask, followed by a drive-in diffusion. Thus, impurity regions 18, that is, first and second sources and first and second drain regions are formed in the surface on the semiconductor substrate 11 on both sides of the first and second gate electrodes 13b and 13c.
In manufacturing a dual-gate MOS of the prior art as described above, the polysilicon 13a doped with the n-type impurities is etched at the same time with that doped with the p-type impurity so as to form the first and second gate electrodes 13b and 13c. The high back pressure is adjusted to above 8 Torr in etching the polysilicon 13a doped with the p-type impurities, so that the top portion of the layer 13a is hotter than the bottom, producing much more polymers at the bottom than in the top portion and especially etching the bottom less. Thus the formed first gate electrode 13b has the trapezoid shape.
Since the polysilicon 13a doped with the n-type impurities is more etched than that doped with the p-type impurities, the bottom of the polysilicon 13a is over-etched to produce the second gate electrode 13c in the vertical form.
A method of manufacturing a semiconductor device according to the prior art presents some disadvantages in that one of the two gate electrodes in a dual-gate MOS is produced in the trapezoid form and that a large phase difference is made between the first and second gate electrodes, deteriorating the characteristic of the dual-gate MOS.